Due to rapid technological advancements in the semiconductor industries and by user demands, the electronic devices are made to be more compact and lightweight. To this end, the multi-chip package having the semiconductor chips mounted on a lead frame for a single package is widely used in devices such as a portable phone requiring miniaturization and lightweight.
FIG. 1 shows the configuration of a conventional multi-chip package, and FIG. 2 shows the configuration of a conventional output enable signal generation circuit.
The conventional multi-chip package shown in FIG. 1 has the first to third slave chips SLAVE_CHIP1, SLAVE_CHIP2, SLAVE_CHIP3 stacked on the master chip MASTER_CHIP.
In the multi-chip package having such a configuration of FIG. 1, data are inputted/outputted through the master chip MASTER_CHIP, and this means that the input/output data paths of the first to third slave chips SLAVE_CHIP1, SLAVE_CHIP1, SLAVE_CHIP3 (for example, DP2, one path from the SLAVE_CHIP3, is shown in FIG. 1) are longer than the data path DP1 of the master chip MASTER_CHIP. Then, for a stable operation, the column address strobe (CAS) latency (CL) of the conventional multi-chip package as shown in FIG. 1 must be set with reference to the longest data path DP2 of the third slave chip SLAVE_CHIP3, and the enable timing of an output enable signal (OE) for the data output in a read operation must be adjusted with reference to the CL set according to the longest data path DP2. For example, when the CL of the master chip MASTER_CHIP is assumed to be 3 tCK, it follows then that the CL of the first slave chip SLAVE_CHIP1 could be 3.5 tCK; the CL of the second slave chip SLAVE_CHIP2 could be 4 tCK; and the CL of the third slave chip SLAVE_CHIP3 could be 4.5 tCK. That is, the CL of each chip is larger as the data path of the chip is longer. To ensure the stable data output operation in such a conventional multi-chip package, the enable timing of the output enable signal (OE) for a data output must be determined according to the largest CL of 4.5 tCK of the third slave chip SLAVE_CHIP3.
FIG. 2 illustrates the configuration of a conventional output enable signal generation circuit implemented in a conventional multi-chip package as shown in FIG. 1.
As shown in FIG. 2, the conventional output enable signal generation unit includes a CAS latency setting unit 10 and an enable setting unit 11. The CAS latency setting unit 10 is configured to receive a mode register set command MRS_CMD inputted for a mode register set and generate an enabled CAS latency signal of CL4.5, the largest among the CL examples above. The enable setting unit 11 is then configured to receive the CAS latency signal CL4.5 and set an enable timing of an output enable signal OE for data output.
To ensure the stable data output of a conventional multi-chip package as shown in FIG. 1, the output enable signal generation circuit shown in FIG. 2 enables the CAS latency signal CL4.5 according to the CL of the third slave chip SLAVE_CHIP3 having the longest data path and determines the enable timing of the output enable signal OE according to the CAS latency signal CL4.5.
Therefore, in case the master chip MASTER_CHIP and the first and second slave chips SLAVE_CHIP1, SLAVE_CHIP2 whose CLs are set to be smaller than the CL of the third slave chip SLAVE_CHIP3, the data is outputted at a timing later than the timing at which the data is actually ready to be outputted.